With the popularization of portable personal devices, there has been an increasing need for memories, and memory technologies have become an important subject in information technology studies.
Read timing generation circuits are widely applied in the design of memories. A read timing generation circuit generates, in response to the input of a multi-bit address signal, read timing related control signals such as Address Transition Detection (ATD), Sense Amplification Precharge Control (SAPC), Sense Out LATch (SOLAT) and Sense Enable (SEN).
In a conventional multi-stage read timing generation circuit, the first stage has a parallel structure. As shown in FIG. 1, the first stage of a read timing generation circuit includes an address transition detection unit 10, an ATD timing generation unit 20 and an ATD decision unit 30. For each bit of an address signal, there is a corresponding stage which independently performs triggering, ATD control timing outputting and ATD decision. That is, the bits of an address signal are entered in parallel into the address transition detection unit 10, the outputs of the address transition detection unit 10 are entered in parallel into the ATD timing generation unit 20, and the outputs of the ATD timing generation unit 20 are entered in parallel into the ATD decision unit 30.
However, the read timing generation circuit has a problem that, with increasing storage capacity and number of bits in an address, since each bit corresponds to a stage, the parallel structure will cause significant increase in the dynamic power consumption of the read timing generation circuit.